The present invention relates generally to semiconductor devices and more particularly to methods and apparatus for electroplating or electrochemical deposition during metal layer deposition in the manufacture of semiconductor devices.
In the manufacture of semiconductor products, individual electrical devices are formed on or in a semiconductor substrate. Thereafter, interconnect processing is performed wherein the electrical devices are interconnected to form electrical circuits. Typically, a multi-level interconnect network is fabricated in layers formed over the electrical devices, by which the device active elements are connected to one another to create the desired circuits. Individual wiring layers within the multi-level network are formed by depositing an insulating or dielectric layer over the discrete devices or over a previous interconnect layer, and patterning and etching cavities such as vias and trenches therein.
Conductive material, such as copper is then deposited into the cavities and the wafer is planarized using chemical mechanical polishing (CMP) to form an interconnect structure. Typical interconnect structures are fabricated using single or dual damascene processes in which trenches and vias are formed (e.g., etched) in a dielectric layer. Copper is then deposited into the trenches and vias and over the insulative layer, followed by CMP planarization to leave a copper wiring pattern inlaid within the dielectric layer trenches and vias. The process is then repeated to form further interconnect layers or levels as needed by which the desired circuit interconnections are made in a multi-level interconnect network.
Diffusion barriers are often formed in the damascene cavities prior to deposition of copper to prevent or reduce diffusion of copper into the dielectric material. Such barriers are typically formed using conductive compounds of transition metals such as tantalum nitride, titanium nitride, and tungsten nitride as well as the various transition metals themselves. Conductive metals, such as aluminum, copper, or the like are then used to fill the cavities after barrier layer formation, where copper is gradually replacing aluminum to improve the conductivity of the interconnect circuits.
The deposition of the conductive copper material in such interconnect processing is generally performed by electroplating, as illustrated in FIGS. 1A-2. This type of processing is sometimes referred to as electrochemical deposition (ECD), and is performed in an electroplating system 2, sometimes referred to as an ECD reactor. In this case, a conductive (e.g., copper) seed layer (not shown) is first formed on a wafer 10 after the diffusion barrier formation, typically via chemical vapor deposition (CVD) or physical vapor deposition (PVD) techniques. In subsequent plating in the system 2, the wafer 10 is electrically coupled with a cathode/wafer holder 4 in a reactor chamber or reservoir 6 filled with electrolytic fluid. The fluid is injected into the reservoir 6 through an inlet port 8, and extracted through an exit port 12.
A voltage is applied across the cathode/wafer holder 4 and an anode 14 via a power source or supply 18 to establish an electric field 16 (e.g., FIG. 1B) in the plating fluid, causing migration and deposition of copper to the wafer workpiece 10 at the wafer holder 4, wherein the wafer 10 operates as a cathode during the plating operation through connection to the wafer holder 4. The initial seed layer thus provides a conductive surface on the wafer 10 such that the electrical connection thereof to the cathode wafer holder 4 causes the electric field lines to end at the wafer 10. The system 2 may further include an anode filter 14a to prevent collection of particulate matter on the cathode 4, which itself is typically fabricated of copper. As illustrated in FIG. 2, the system 2 may further include a fluid dispersion disk 20 with spirally disposed holes 22 to direct the electrolytic plating fluid to the wafer 10 in a controlled fashion.
In a typical ECD process, the plated upper surface of the wafer 10 is located so as to face the anode 14 in the reservoir. The wafer holder structure 4 electrically contacts the plated upper wafer surface at the peripheral edges 10a thereof. However, because the seed layer is of finite thickness, a non-zero resistance exists between interior points 10b on the plated wafer surface and the edge points 10a at which electrical contact is made to the cathode wafer holder clamp 4. The seed layer thus has a non-uniform voltage potential which is positive at the center 10b and negative at the wafer edges 10a, resulting in higher current densities near the wafer edge 10a than at the center 10b, particularly at the beginning of the plating process.
The rate of copper deposition during electroplating at a given point on the wafer surface is generally proportional to the current density thereat. Thus, the deposited copper from the ECD process is thinner at the center 10b than at the edges 10a, due to the seed layer resistance. This is illustrated in a graph 30 in FIG. 1B of deposited copper thickness (y axis) versus position (x axis), wherein the curve 32 has a concave profile. Although subsequent copper deposition in the ECD reservoir 6 reduces this resistance disparity, the initial electrode-position rate in particular is higher at the edges 10a than at the interior 10b of the wafer 10. Thus, the initial deposition causes a concave copper thickness profile 32, which is built up even when the inner and outer deposition rates become closer.
Recent scaling efforts in semiconductor devices have resulted in smaller feature sizes and closer feature spacing. Seed layer thicknesses continue to be reduced accordingly, to avoid necking effects and other problems in filling the gaps between such closely spaced features. As a result, the initial seed layer resistance between the wafer center 10b and the edges 10a continues to increase due to seed layer thinning, thereby worsening the copper deposition uniformity problem. In addition, wafer sizes are increasing, for example, from 200 mm to newer 300 mm diameter wafers. This causes higher voltage drops between the wafer center 10b and edges 10a for a given seed layer thickness and resistivity. Thus, adjustment in the seed layer deposition process step has limited impact on combating the non-uniform deposited copper thickness in interconnect process steps employing electroplating.
Furthermore, conventional CMP processes often suffer from dishing and/or erosion difficulties, wherein material is removed in a non-uniform manner. For example, a CMP process may remove more material from the center 10b of the wafer 10 than from the edges 10a, thereby compounding the ECD deposition non-uniformities. Thus, the ECD process provides thick copper at the edges 10a and thin copper at the center 10b, after which the wafer 10 is planarized by CMP processing which removes material from the (thin) center 10b faster than from the (thick) edges 10a. 
While CMP process chemistry and other parameters may be adjusted to reduce material removal non-uniformities, it is generally desirable to provide an electroplating process by which a copper layer of uniform or controllable thickness is deposited prior to CMP processing. Absent such, current efforts include depositing more copper (e.g., lengthening the electroplating process) to ensure complete filling of the thin inner regions 10b of the wafer with sufficient process margin to compensate for the faster CMP removal rate at the center 10b. The CMP planarization, in turn, must be performed for longer periods of time to ensure exposure of dielectric material between the filled trenches at the edges 10a of the wafer 10. Both such process refinements result in a net increase in processing time per wafer (e.g., and thus reduced throughput), which is undesirable.
Furthermore, where it is known that a particular CMP process has a higher material removal rate at the inner regions 10b than at the outer regions 10a, which cannot be further optimized, it may be desirable to deposit copper via an electroplating process providing thicker copper in the center 10b and thinner copper at the edges 10a. However, as mentioned above, conventional copper electroplating techniques do not offer such options. Thus, there remains a need for improved methods and apparatus for electroplating semiconductor wafers and other devices using electroplating, by which the aforementioned difficulties may be mitigated or overcome.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention relates to electroplating conductive films on semiconductor wafers, such as copper deposition during back end interconnect processing in the manufacture of semiconductor devices. The invention may be employed to facilitate adjustment and/or control of electric fields used to plate the wafers, by which improved plating current density uniformity and hence deposition fill uniformity and/or controllability may be facilitated in depositing copper or other materials. Improved fill uniformity, in turn, facilitates reduction in deposition layer thicknesses, and corresponding reduction in the amount of material that needs to be removed in subsequent planarization processing, whereby improved process throughput may be achieved.
One aspect of the invention provides electroplating systems and apparatus therefor, in which a field adjustment plate is located in a reservoir between a cathode and an anode, having plugable apertures to influence the electric field used in the plating process. Plates are presented having one or more apertures, which may be selectively plugged to adjust the electrical fields and hence the current density and metal deposition rates during plating. Plugs are provided, which may extend past the plate surfaces in the direction of the wafer workpiece, wherein the amount of such extension and the shape of the extended portions of the plugs may be used to influence or control the electric field during plating. The field adjustment plate and the plugs may be fashioned of any dielectric type material, such as plastics, by which portions of the electric field between the plating process cathode and anode can be inhibited or adjusted.
Systems employing the various aspects of the invention may selectively employ one or more such plugs in various apertures in the plate, to achieve a desired electric field during plating, and the number and location of plugged apertures may be easily adjusted for a different process recipe. Other aspects of the invention provide electroplating methodologies in which one or more plate apertures is selectively plugged to modify or control electric fields used to deposit copper and other conductive materials in the manufacture of semiconductor and other devices. The invention may thus be employed for spatial control over deposition thickness, even where initial seed layer resistance is relatively high.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.